1. Field of the Invention
The present invention relates to a trigonometric function arithmetic processor, and more specifically to a trigonometric function arithmetic processor for use in computers.
2. Description of Related Art
Trigonometric functions such as sin .theta. and cos .theta. are function having a period of 2.pi. namely 360 degrees. An ability of calculating the trigonometric functions is one function indispensable to computers processing scientific and technical computations.
Hitherto, as a means for obtaining the value of the trigonometric function, there have been known to use rational function approximations such as Taylor expansion which can be expressed as EQU sin .theta.=.theta.-.theta..sup.3 /3!+.theta..sup.5 /5!-.theta..sup.7 /7! . . . (1)
series fraction expansion, and Chebyshev expansion. However, these methods need a number of multiplication operations and division operations and therefore, require a long operation time. In addition, the satisfied degree of precision cannot be obtained.
Further, a so-called "CORDIC" (coordinate rotation digital computer) arithmetic is known as a trigonometric function arithmetic operation method suitable to microprogram controlled computers. This method can be executed by using addition, subtraction and right shift, and therefore, can be efficiently executed in computers which do not have a high speed multiplication unit.
Here, an arithmetic principle of the CORDIC will be described below with reference to a case in which the values of sin .theta. and cos .theta. are obtained with the precision of n-digits in a binary notation.
An angle .theta. can be expressed as follows, by using a constant "r.sub.k " and a sequence of numbers {a.sub.k }: EQU .theta.=a.sub.0 .times.r.sub.0 +a.sub.1 .times.r.sub.1 +a.sub.2 .times.r.sub.2 . . . a.sub.n-1 .times.r.sub.n-1 +.epsilon.(2)
where EQU r.sub.k =arctan (2.sup.-k) (3) EQU a.sub.k ={+1, -1} (4)
The sequence of numbers {a.sub.k } can be spontaneously determined in accordance with a method similar to the division of a non-restoring method. Therefore, the process for determining the sequence of numbers {a.sub.k } will be called a "pseudo-division" hereinafter.
Here, according to the theorem of addition,
in the case of a.sub.k =+1 EQU .PSI..sub.k+1 =.PSI..sub.k +r.sub.k EQU cos (.PSI..sub.k+1)=R.sub.k (cos .PSI..sub.k -2.sup.-k .times.sin .PSI..sub.k) (5) EQU sin (.PSI..sub.k+1)=R.sub.k (sin .PSI..sub.k -2.sup.-k .times.cos .PSI..sub.k) (6) PA0 in the case of a.sub.k =-1 EQU .PSI..sub.k+1 =.PSI..sub.k -r.sub.k EQU cos (.PSI..sub.k+1)=R.sub.k (cos .PSI..sub.k +2.sup.-k .times.sin .PSI..sub.k) (7) EQU sin (.PSI..sub.k+1)=R.sub.k (sin .PSI..sub.k +2.sup.-k .times.cos .PSI..sub.k) (8) PA0 where ##EQU2##
Thus, the values of sin .theta. and cos .theta. are obtained by repeatedly executing the above operation so that .PSI..sub.k gradually approach .theta.. This process will be called a "pseudo-multiplication".
The final sin (.PSI..sub.k) and cos (.PSI..sub.k) is multiplied by K, and therefore, it is necessary to correct them. ##EQU3##
Now, explanation will be made on the algorithm of the CORDIC.
(1) It is initialized to x.sub.0 =1/K, y.sub.0 =0, v.sub.0 =.theta. (0.ltoreq..theta.&lt;.pi./2). Here, K is a constant which fulfils the equation (10).
(2) The following step (3) is repeated for k=0, 1, 2, . . . , (n-1).
(3) If v.sub.k .gtoreq.0, it is assumed that a.sub.k =+1, and if v.sub.k &lt;0, it is assumed that a.sub.k =-1, EQU x.sub.k+1 =x.sub.k -a.sub.k .times.2.sup.-k .times.y.sub.k ( 11) EQU y.sub.k+1 =y.sub.k +a.sub.k .times.2.sup.-k .times.x.sub.k ( 12) EQU v.sub.k+1 =v.sub.k -a.sub.k .times.r.sub.k ( 13)
where r.sub.k is a constant fulfilling the equation (3).
(4) cos .theta.=x.sub.n and sin .theta.=y.sub.n can be simultaneously obtained.
Referring to FIG. 1, there is shown one example of a pipeline arithmetic processor embodying the algorithm of the CORDIC. The shown processor comprises a cascaded operational units 41, 42, . . . , 49 which have the same construction, and constructs n stages of pipeline.
The operational unit 41 has n-bit registers 411, 412 and 413 which respectively store three kinds of variables x.sub.k, y.sub.k, and v.sub.k in a binary notation. A pair of shifters 414 and 415 are connected to outputs of the registers 412 and 411, respectively. These shifters function to rightwardly shift the received data of n-bits by k bits. In addition, there is provided a constant generator 416 for generating a n-bit constant r.sub.k defined in the above mentioned equation (3). The outputs of the three registers 411, 412 and 413 and the outputs of the shifters 414 and 415 and the constant generator 416 are applied to three n-bit adder/subtracters 417, 418 and 419, as shown.
In the shown processor, the operational units 41, 42, . . . , 49 execute the operation the above mentioned algorithm step (3) for k=0, 1, . . . , (n-1).
Thus, in a first step [A], 1/K, 0 and .theta. are set as initial values to the registers 411, 412 and 413.
In a second step [B], the variable is made to k=0 in the operational unit 41. Therefore, the variable x.sub.k of the equation (11) is stored in the register 411, the variable y.sub.k of the equation (12) is stored in the register 412, and the variable v.sub.k of the equation (13) is stored in the register 413.
The shifters 414 and 415 operate to rightwardly shift the output data from the registers 412 and 411 by k bits. Namely, the output data from the registers 412 and 411 are respectively multiplied by 2.sup.-k. At this time, if the sign bit of the register 413 is positive, a.sub.k =+1, and therefore, the adder/subtracters 417 and 419 are controlled to execute the subtraction, and the adder/subtracter 418 is controlled to execute the addition. On the other hand, if the sign bit of the register 413 is negative, since a.sub.k =-1, the adder/subtracters 417 and 419 are controlled to execute the addition, and the adder/subtracter 418 is controlled to execute the subtraction.
Thus, the outputs of the three adder/subtracters 417, 418 and 419 are outputted as the variables x.sub.k+1, y.sub.k+1, and v.sub.k+1 to three registers 421, 422 and 423 of the next stage operational unit 42 which respectively correspond to the registers 411, 412 and 413 of the first stage operational unit 41.
Thereafter, in a third step [C], the above mentioned operation (B) are sequentially executed for k=1, 2, . . . , (n-1) in the operational units 42, . . . , 49.
In a fourth step [D], the final stage operational unit 49 respectively outputs x.sub.n =cos .theta. and y.sub.n =sin .theta. from adder/subtracters (not shown) corresponding to the adder/subtracters 417 and 418 of the first stage operational unit 41.
If an angle .theta. is inputted to the register 413 for each clock, the values of cos .theta. and sin .theta. are outputted from the final stage operational unit 49 for every clock. But, assuming that the operation of each of the operational units 41 to 49 needs one clock and the stage number of the operational units 41 to 49 is "n", n clocks are required from the input of the angle .theta. to the output of the values of cos .theta. and sin .theta..
The above mentioned trigonometric function arithmetic processor is disadvantageous in the followings:
First, the conventional trigonometric function arithmetic processor requires a large amount of hardware. For example, the above mentioned trigonometric function arithmetic processor needs 2n shifters which can shift data of n-bits by k bits and 3n adder/subtracters. If these circuit elements are assembled on an large scale integrated circuit, since the shifter having a large shift bit number requires a large area, the trigonometric function arithmetic processor will be inevitably of a large size.
Particularly, in order to realize the operation at a high degree of precision, an area for barrel shifters and adder/subtracters is significantly increased. For example, in order to obtain the precision of 32 bits in binary notation, there are required 96 adder/subtracters of 32 bits and a pair of 32-bit shifters which can rightwardly shift by 0, 1, 2, . . . , 31 bits, respectively (64 in total).
Secondly, the conventional trigonometric function arithmetic processor can obtain a sufficient degree of precision in the result of the operation. The larger the value "k" is, the value "r.sub.k " in the equation (6) will become small, and therefore, the digit number of the significant figures will be decreased. As a result, an rounding error is accumulated at the LSB of the data.